1. Field of the Invention
The invention relates to the design of electronic circuits and more particularly to optimized mapping of a higher level design to multiple cell libraries.
2. Description of the Related Art
Synthesis of an integrated circuit design involves a process of translation of a behavioral description of the design to a structural description of the design optimized according to one or more constraints. A designer ordinarily sets forth a behavioral description of a design in a high level descriptive language such as Verilog or VHDL, or describes a model of the design in the C or C++ programming language, for example. In general, a behavioral description provides a register transfer level (RTL) model of a design is a description of a circuit design in terms of data flow between registers, which store information between clock cycles in a circuit. An RTL description specifies what and where this information is stored and how it is passed through the circuit during its operation.
In one aspect, a synthesis process converts a behavioral description of a design to a structural description in terms of a netlist, for example. Optimization techniques typically are employed in the conversion of the behavioral description to the gate level description. In another aspect, a synthesis process, maps a design to a cell library. A cell represents a circuit element that is available in a particular implementation technology, and a cell library is a collection of these cells. A cell library may comprise a few hundred cells corresponding to primitive circuits, such as inverters, NAND gates, NOR gates and possibly to more complex Boolean circuits and perhaps, to sequential elements like latches and flip-flops, for which optimized models have been designed for a particular purpose, such as for operation at a particular voltage level, for example. Optimization techniques also typically are employed in the mapping of gates in a netlist to cells in a technology model.
Multiple Supply Multiple Voltage (MSMV) is an architectural-level power optimization technique to reduce dynamic power (also known as active power) dissipation in integrated circuit devices. The MSMV design style exploits the well-known quadratic relationship between supply voltage and dynamic power. Pedram, M.; Abdollahi, A., Low-power RT-level synthesis techniques: a tutorial, IEEE Proc. Comp. Dig. Tech., May 2005. Advanced techniques such shutoff and wakeup, multiple voltage islands Sun Microsystems, “UltraSPARC T1 Overview,” at (worldwide web).sun.com/processors/UltraSPARC-T1, dynamic voltage scaling, Lackey, D. E et al, “Managing power and performance for system-on-chip designs using Voltage Islands,” ICCAD 2002; Montanaro, J. et al, “A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor,” Solid-State Circuits, IEEE Journal of, vol. 31, no. 11, pp. 1703-1714, November 1996, have been developed to address these issues.
A MSMV design typically includes multiple blocks or regions having different supply voltages such that the overall chip power dissipation can be minimized while balancing other performance targets such as timing area requirements. In general, switching power dissipation is proportional to the square of the supply voltage, the lower the supply voltage, the lesser the power dissipation. Thus, a reduction in supply voltage leads to a corresponding reduction in switching power dissipation. However, a lower the supply voltage also results in a slower circuit. Therefore a challenge has been to reduce the power dissipation without reducing circuit performance.
In general, MSMV is applicable in any situation in which a slow block in a design is interfaced to a faster block in the design. For example, a typical system on a chip (SoC) includes several blocks and also may have multiple clock domains, with the domains possibly operating at different frequencies. To save active power, blocks that are not performance critical can be clocked at a lower frequency than performance critical blocks. This leads to a linear reduction in power for those blocks. While power consumption is reduced due to frequency reduction, it is possible to reduce supply voltage further. Since gate delays increase as the supply voltage decreases, for any target frequency, it is possible to discover the minimum supply voltage that is required to sustain that target frequency. Since active power depends on the square of supply voltage, even small reductions in supply voltage can result in large reductions in active power.
MSMV also can be applied in situations in which there is only one clock domain. For instance, consider two blocks with a producer-consumer relationship. One example is a decryption block whose data is consumed by a CPU block. In that situation, the same clock could drive both blocks. If the decryption algorithm is sufficiently simple, it is possible to have large positive slack in the decryption block while the CPU block has zero slack (timing is just met). In such a situation, the decryption block cannot be clocked at a lower frequency, because both blocks are driven by the same clock. But the positive slack in the decryption block can be exploited to reduce the supply voltage to the decryption block.
MSMV also is useful is when a pipelined block is interfaced to a non-pipelined block. Pipelined blocks are specifically designed to operate at high frequencies. Hence, the pipelined block often will have significant positive slack. Therefore, supply voltage to the pipelined block sometimes can be reduced to use up all the positive slack, resulting in power savings.
During synthesis of a MSMV design, gates in a design that operate at different voltages are mapped to different library cells. For instance, one library cell may have timing and power characteristics for one supply voltage used in the design, and another library cell may have timing and power characteristics for another supply voltage in the design. A gate in the design may be mapped to one or the other of the two library cells depending upon the supply voltage at which the gate to be mapped operates. Library vendors often characterize cells at different voltages and create separate libraries for each voltage. Thus, cells corresponding to the same functionality, or logic gate, at two different voltages would be found in two different libraries.
FIG. 1 is an illustrative flow diagram of a prior technology mapping and optimization process 100. The process 100 involves multiple mapping and optimization passes 108-1 to 108-n. Different passes map different blocks of the a design to different libraries. In step 102, an RTL description of the design is obtained, i.e., an RTL file is stored in memory accessible to the processor performing the mapping and optimization process. In step 104, the design is partitioned into blocks that use one supply voltage each. In step 106, block level timing constraints are derived. Next, multiple mapping and optimization passes 108-1 to 108-n are performed. In this example, the design is assumed to have been partitioned into n blocks, and a separate mapping and optimization pass is performed for each block. In a first step, 110-1 to 110-n of each pass 108-1 to 108-n, respective design information for the block (e.g., RTL) and a respective library to be used for the block (i.e., the cell library characterized for the supply voltage used by the block) is accessed. In a second step, 112-1 to 112-n of each pass 108-1 to 108-n, the respective design information for the respective block is mapped to the appropriate cells of the respective library. The result of the multiple passes 108-1 to 108-n is multiple blocks that have been mapped to multiple libraries. In step 114, the multiple mapped blocks are reassembled into the single design. In decision step 116 and analysis is made as to whether the reassembled design meets the constraints set in step 106. If yes, then the process stops. If no, then in decision step 120, a determination is made as to whether to perform a different partition. If yes, then the process returns to step 104. If no, then the process returns to step 106.
While prior approaches to mapping and optimization of MSMV designs generally have been acceptable, there have been drawbacks. For instance, as illustrated in the above example, each block of the design that used a different supply voltage typically was mapped and optimized in a separate synthesis pass. Thus, technology mapping of the entire chip design did not occur a single run. Moreover, a user could not run timing or power analysis at the full chip level during mapping and optimization to check whether timing and power goals had been met.
Also, the prior approach is inefficient since multiple passes typically will be required to meet design targets. The process involves partitioning the design into smaller blocks and deriving timing and power constraints for each block. The quality of the derived timing and power constraints for each block influences the quality of the overall result. The challenge is to apportion timing and power constraints across the multiple blocks so that the resultant design meets design targets. This can be a difficult challenge. If block-level target constraints turn out to be too tight, then the resulting IC chip will have a larger area and consume more power than an optimal solution. If block-level target constraints are too lenient, then timing will not be met at the top-level (when the blocks are reassembled), and another iteration of time budgeting and synthesis will be required. Moreover, since blocks are optimized individually in separate passes, even if each block meets its individual timing and power constraints, the overall reassembled design still may not meet the design targets, since the blocks are not optimized relative to each other.
Thus, there has been a need for improvements in the mapping and optimization of a circuit design to multiple cell libraries. The present invention meets this need.